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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
MC54/74HC589A
J SUFFIX CERAMIC PACKAGE CASE 620-10
1
8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with 3-State Output
High-Performance Silicon-Gate CMOS
The MC54/74HC589A is similar in function to the HC597, which is not a 3-state device. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. This device consists of an 8-bit storage latch which feeds parallel data to an 8-bit shift register. Data can also be loaded serially (see Function Table). The shift register output, QH, is a three-state output, allowing this device to be used in bus-oriented systems. The HC589A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 526 FETs or 131.5 Equivalent Gates
16
16 1
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
16 1
DT SUFFIX TSSOP PACKAGE CASE 948F-01
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP
LOGIC DIAGRAM
SERIAL DATA INPUT SA 14 B A B PARALLEL DATA INPUTS C D E F G H LATCH CLOCK 15 1 2 3 4 5 6 7 12 9 QH SERIAL DATA OUTPUT DATA LATCH SHIFT REGISTER VCC = PIN 16 GND = PIN 8 C D E F G H GND
PIN ASSIGNMENT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A SA SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK SHIFT CLOCK OUTPUT ENABLE QH
SHIFT CLOCK SERIAL SHIFT/ PARALLEL LOAD OUTPUT ENABLE
11 13 10
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
(c) Motorola, Inc. 1995
1
REV 0
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MOTOROLA Symbol Vin, Vout Symbol Symbol VCC Vout Tstg ICC Iout VCC Vin PD TL VOH tr, tf Iin VOL TA VIH VIL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC54/74HC589A
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
(Figure 1)
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vin = VIH |Iout| 20 A
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2
- 55
Min
2.0
Value
v 2.4 mA v 6.0 mA v 7.8 mA v 2.4 mA v 6.0 mA v 7.8 mA
0 0 0 0 75 35 20 260 300 750 500 450
+ 125
1000 TBD 500 400
VCC
Max
6.0
VCC V
3.0 4.5 6.0
2.0 4.5 6.0
3.0 4.5 6.0
2.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
0.26 0.26 0.26
2.48 3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.33 0.33 0.33 2.34 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9
v
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
0.40 0.40 0.40 2.20 3.70 5.20 1.9 4.4 5.9 0.1 0.1 0.1
v
Unit
V V V V
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NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL tPZL, tPZH tPLZ, tPHZ fmax CPD Cout ICC IOZ Cin Iin Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current Maximum Input Leakage Current Power Dissipation Capacitance (Per Package)* Maximum Three-State Output Capacitance (Output in High-Impedance State) Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 8) Maximum Propagation Delay, Output Enable to QH (Figures 3 and 9) Maximum Propagation Delay, Output Enable to QH (Figures 3 and 9) Maximum Propagation Delay, Shift Clock to QH (Figures 2 and 8) Maximum Propagation Delay, Latch Clock to QH (Figures 1 and 8) Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 8) Parameter Parameter Vin = VCC or GND Iout = 0 A Vin = VCC or GND
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Propagation Delay, Serial Shift/Parallel Load to QH (Figures 4 and 8)
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND
Test Conditions
3 VCC V VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 6.0 6.0 -- -- - 55 to 25_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 0.5 0.1 60 TBD 12 10 6.0 TBD 30 35 150 80 27 23 150 80 27 23 160 90 30 25 160 90 30 25 175 100 40 30 15 10 4 Guaranteed Limit Guaranteed Limit 5.0 1.0 75 TBD 15 13 4.8 TBD 24 28 170 100 30 25 170 100 30 25 200 130 40 30 200 130 40 30 225 110 50 40 15 10 40 50 1.0 90 TBD 18 15 4.0 TBD 20 24 10 200 130 40 30 200 130 40 30 240 160 48 40 240 160 48 40 275 125 60 50 160 15 10
v 85_C v 125_C
v 85_C v 125_C
MC54/74HC589A
MOTOROLA MHz Unit Unit A A A pF pF pF ns ns ns ns ns ns
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
MC54/74HC589A
Symbol
tr, tf
tsu
tsu
tsu
tw
tw
tw
th
th
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Serial Shift/Parallel Load (Figure 4)
Minimum Pulse Width, Latch Clock (Figure 1)
Minimum Pulse Width, Shift Clock (Figure 2)
Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 6)
Minimum Hold Time, Latch Clock to A-H (Figure 5)
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 7)
Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 6)
Minimum Setup Time, A-H to Latch Clock (Figure 5)
Parameter
4 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 TBD 500 400 80 TBD 16 14 80 TBD 16 14 75 TBD 15 13 25 TBD 5 5 100 TBD 20 17 100 TBD 20 17 100 TBD 20 17 5 5 5 5
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1000 TBD 500 400 95 TBD 19 16 30 TBD 6 6 100 TBD 20 17 100 TBD 20 17 125 TBD 25 21 125 TBD 25 21 125 TBD 25 21 5 5 5 5 1000 TBD 500 400 40 TBD 8 7 120 TBD 24 20 120 TBD 24 20 150 TBD 30 26 150 TBD 30 26 150 TBD 30 26 5 5 5 5 110 TBD 23 19 Unit ns ns ns ns ns ns ns ns ns
MC54/74HC589A
FUNCTION TABLE
Inputs Output Enable H L L L Serial Shift/ Parallel Load X H L H L, H, L, H, Latch Clock X Shift Clock X L, H, X L, H, Serial Input SA X X X X Parallel Inputs A-H X a-h X X Data Latch Contents X a-h U U Resulting Function Shift Register Contents X U LRN SRN U Output QH Z U LRH U
Operation Force output into high impedance state Load parallel data into data latch Transfer latch contents to shift register Contents of input latch and shift register are unchanged Load parallel data into data latch and shift register Shift serial data into shift register Load parallel data in data latch and shift serial data into shift register
L
L
X
X
a-h
a-h
a-h
h
L L
H H
X
D D
X a-h
* a-h
SRA = D, SRN SRN+1 SRA = D, SRN SRN+1
SRG SRH SRG SRH
LR = latch register contents SR = shift register contents a-h = data at parallel data inputs A-H D = data (L, H) at serial data input SA
U = remains unchanged X = don't care Z = high impedance * = depends on Latch Clock input
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC589A
SWITCHING WAVEFORMS
tr LATCH CLOCK 90% 50% 10% tw tPLH QH 90% 50% 10% tTLH tTHL tPHL tPLH QH 50% tPHL tf VCC GND SHIFT CLOCK 50% GND tw 1/fmax VCC
Figure 1. (Serial Shift/Parallel Load = L)
Figure 2. (Serial Shift/Parallel Load = H)
OUTPUT ENABLE
VCC 50% GND tPZL tPLZ HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE QH SERIAL SHIFT/ PARALLEL LOAD tw 50% tPLH 50% 50% GND tPHL VCC
QH
50% tPZH tPHZ
QH
50%
Figure 3.
Figure 4.
DATA VALID A-H VCC 50% GND tsu LATCH CLOCK th 50% SHIFT CLOCK SA
DATA VALID VCC 50% GND tsu th 50%
Figure 5.
Figure 6.
TEST POINT VCC 50% GND tsu SHIFT CLOCK 50% * Includes all probe and jig capacitance OUTPUT DEVICE UNDER TEST CL*
SERIAL SHIFT/ PARALLEL LOAD
Figure 7.
Figure 8. Test Circuit
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC589A
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
* Includes all probe and jig capacitance
Figure 9.
PIN DESCRIPTIONS
DATA INPUTS A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7) Parallel data inputs. Data on these inputs are stored in the data latch on the rising edge of the Latch Clock input. SA (Pin 14) Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input if Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low. CONTROL INPUTS Serial Shift/Parallel Load (Pin 13) Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the data latch. Shift Clock (Pin 11) Serial shift clock. A low-to-high transition on this input shifts data on the serial data input into the shift register and data in stage H is shifted out QH, being replaced by the data previously stored in stage G. Latch Clock (Pin 12) Data latch clock. A low-to-high transition on this input loads the parallel data on inputs A-H into the data latch. Output Enable (Pin 10) Active-low output enable A high level applied to this pin forces the QH output into the high impedance state. A low level enables the output. This control does not affect the state of the input latch or the shift register. OUTPUT QH (Pin 9) Serial data output. This pin is the output from the last stage of the shift register. This is a 3-state output.
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC54/74HC589A
TIMING DIAGRAM
SHIFT CLOCK SERIAL DATA INPUT, SA
OUTPUT ENABLE SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK
A B
L L
H L
L L
L L
C D
L L
H L
L L
L L
PARALLEL DATA INPUTS
E
L
H
L
H
F G
L L
H L
L L
H L
H
L
QH
RESET LATCH LOAD LATCH PARALLEL LOAD AND SHIFT REGISTER SHIFT REGISTER
MOTOROLA
EEEEE EEEEE EEEEE EEEEE
H
HIGH IMPEDANCE
H L H H L H L L H L L L
H L
H
H
H
HH
SERIAL SHIFT
SERIAL SHIFT
SERIAL SHIFT
SERIAL SHIFT
LOAD LATCH
PARALLEL LOAD SHIFT REGISTER
PARALLEL LOAD, LATCH AND SHIFT REGISTER
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC589A
LOGIC DETAIL
10 14 11
OUTPUT ENABLE SA SHIFT CLOCK
SERIAL SHIFT/ 13 PARALLEL LOAD LATCH CLOCK A 12 15 STAGE A D C Q D S CQ R
STAGE B B 1 D C Q D S CQ R
PARALLEL DATA INPUTS
C
2
STAGE C*
D
3
STAGE D*
E
4
STAGE E*
F
5
STAGE F*
G
6
STAGE G* STAGE H VCC D S CQ R 9 QH
H
7
D C
Q
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
High-Speed CMOS Logic Data DL129 -- Rev 6
9
MOTOROLA
MC54/74HC589A
OUTLINE DIMENSIONS
-A -
16 9
J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V
-B - C L
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-T
SEATING - PLANE
N E F G D 16 PL 0.25 (0.010)
M
K M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
-A -
16 9
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
MOTOROLA
10
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC589A
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
K1
2X
L/2
16
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
11
*MC54/74HC58A9/D*
EE CC EE CC EE CC EE CC
-W-
MC54/74HC58A9/D MOTOROLA

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